Semiconductor package having a chip carrier with a pad offset feature

US11984392B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Chee Yang Ng · Kluang, MY
• Stefan Woetzel · Erfurt, DE
• Edward Fuergut · Nuremberg, DE
• Thai Kee Gan · Melaka City, MY
• Chee Hong Lee · 流花街道, CN
• Jayaganasan Narayanasamy · Pantai Belimbing, MY
• Ralf Otremba · Kaufbeuren, DE

Key dates

• Filing date: Aug 27, 2021
• Grant date: May 14, 2024
• Expiry date: Jun 24, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/13091
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.