Memory device
US11985822B2 · kind B2 · utility
0Cited by
10References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2020 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Oct 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.