Semiconductor device patterning methods
US11987875B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Jan 12, 2023 |
| Grant date | May 21, 2024 |
| Priority date | — |
| Expiry date | Jan 12, 2043 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC23C22/82
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Methods of patterning semiconductor devices comprising selective deposition methods are described. A blocking layer is deposited on a metal surface of a semiconductor device before deposition of a dielectric material on a dielectric surface. Methods include exposing a substrate surface including a metal surface and a dielectric surface to a heterocyclic reactant comprising a headgroup and a tailgroup in a processing chamber and selectively depositing the heterocyclic reactant on the metal surface to form a passivation layer, wherein the heterocyclic headgroup selectively reacts and binds to the metal surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.