John Sudijono
66Patents
13h-index
95Co-inventors
87Inventor score
Filing activity: Oct 13, 1998 → Aug 10, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6706625B1 | Copper recess formation using chemical process for fabricating barrier cap for lines and vias | Electricity | 123 | Expired |
| US6211040A | Two-step, low argon, HDP CVD oxide deposition process | Electricity | 42 | Expired |
| US6787452B2 | Use of amorphous carbon as a removable ARC material for dual damascene fabrication | Emerging Cross-Sectional Technologies | 37 | Expired |
| US6683002B1 | Method to create a copper diffusion deterrent interface | Electricity | 29 | Expired |
| US6355581B1 | Gas-phase additives for an enhancement of lateral etch component during high density plasma film deposition to improve film gap-fill capability | Electricity | 27 | Expired |
| US8177993B2 | Apparatus and methods for cleaning and drying of wafers | Electricity | 27 | Active |
| US7524755B2 | Entire encapsulation of Cu interconnects using self-aligned CuSiN film | Electricity | 26 | Expired |
| US6378759B1 | Method of application of conductive cap-layer in flip-chip, COB, and micro metal bonding | Electricity | 25 | Expired |
| US6583069B1 | Method of silicon oxide and silicon glass films deposition | Performing Operations; Transporting | 25 | Expired |
| US6720204B2 | Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding | Electricity | 23 | Expired |
| US6417088B1 | Method of application of displacement reaction to form a conductive cap layer for flip-chip, COB, and micro metal bonding | Electricity | 21 | Expired |
| US6340608B1 | Method of fabricating copper metal bumps for flip-chip or chip-on-board IC bonding on terminating copper pads | Electricity | 14 | Expired |
| US6500771B1 | Method of high-density plasma boron-containing silicate glass film deposition | Electricity | 14 | Expired |
| US6475810B1 | Method of manufacturing embedded organic stop layer for dual damascene patterning | Electricity | 13 | Expired |
| US7052932B2 | Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication | Emerging Cross-Sectional Technologies | 13 | Expired |
| US7256084B2 | Composite stress spacer | Electricity | 12 | Expired |
| US6143598A | Method of fabrication of low leakage capacitor | Electricity | 11 | Expired |
| US7445978B2 | Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS | Electricity | 11 | Expired |
| US6451687B1 | Intermetal dielectric layer for integrated circuits | Electricity | 10 | Expired |
| US6429117B1 | Method to create copper traps by modifying treatment on the dielectrics surface | Emerging Cross-Sectional Technologies | 8 | Expired |
| US6872633B2 | Deposition and sputter etch approach to extend the gap fill capability of HDP CVD process to ≦0.10 microns | Electricity | 8 | Expired |
| US6069082A | Method to prevent dishing in damascene CMP process | Electricity | 7 | Expired |
| US6350689B1 | Method to remove copper contamination by using downstream oxygen and chelating agent plasma | Emerging Cross-Sectional Technologies | 6 | Expired |
| US7538353B2 | Composite barrier/etch stop layer comprising oxygen doped SiC and SiC for interconnect structures | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6705512B2 | Method of application of conductive cap-layer in flip-chip, cob, and micro metal bonding | Electricity | 6 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.