Patent · US Active

Data bridge for interfacing source synchronous datapaths with unknown clock phases

US11989148B2 · kind B2 · utility

0Cited by

12References

16Claims

0Family size

Assignee

STMicroelectronics International N.V. · NL

Inventors

Ankur Bal · Ghaziabad, IN
Rupesh SINGH · Ghaziabad, IN

Key dates

Filing date	Dec 10, 2021
Grant date	May 21, 2024
Priority date	—
Expiry date	Jan 18, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/037
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.