Stress relief in semiconductor wafers
US11990425B2 · kind B2 · utility
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20Claims
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Assignee
Inventors
Key dates
| Filing date | Aug 18, 2021 |
| Grant date | May 21, 2024 |
| Priority date | — |
| Expiry date | May 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This disclosure describes a method for fabricating a plurality of semiconductor devices in a semiconductor wafer includes: bowing a semiconductor wafer including a substrate by covering the substrate with a strained layer; forming trenches at locations in scribe lines of the semiconductor wafer, the scribe lines identifying areas between adjacent dies on the semiconductor wafer; and reducing the bowing of the semiconductor wafer by filling the trenches with a stress-compensation material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.