DRAM circuitry and method of forming DRAM circuitry

US11991877B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Toshihiko Miyashita · Kawasaki, JP
• Dan M. Mocuta · Herent, BE

Key dates

• Filing date: Jul 29, 2021
• Grant date: May 21, 2024
• Expiry date: Mar 9, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

DRAM circuitry comprises a memory array comprising memory cells individually comprising a transistor and a charge-storage device. The transistors individually comprise two source/drain regions having a gate there-between that is part of one of multiple wordlines of the memory array. One of the source/drain regions is electrically coupled to one of the charge-storage devices. The other of the source/drain regions is electrically coupled to one of multiple sense lines of the memory array. Peripheral circuitry comprises wordline-driver transistors having gates which individually comprise one of the wordlines and comprises sense-line-amplifier transistors having gates which individually comprise one of the sense lines. The sense-line-amplifier transistors and the wordline-driver transistors individually are a finFET having at least one fin comprising a channel region of the respective finFET. The sense-line-amplifier transistors and the wordline-driver transistors individually comprise two source/drain regions that individually comprise conductively-doped epitaxial semiconductor material that is adjacent one of two laterally-opposing sides of the at least one fin in a vertical cross-se…