V-NAND stacks with dipole regions
US11997849B2 · kind B2 · utility
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4References
19Claims
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Key dates
| Filing date | May 25, 2021 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Feb 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.