Self-annealing data storage system
US12002513B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2022 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Feb 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/324
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.