Gary B. Bronner
128Patents
27h-index
112Co-inventors
93Inventor score
Filing activity: Nov 2, 1990 → Feb 27, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6566177B1 | Silicon-on-insulator vertical array device trench capacitor DRAM | Electricity | 181 | Expired |
| US5606188A | Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory | Electricity | 162 | Expired |
| US7470570B2 | Process for fabrication of FinFETs | Electricity | 132 | Active |
| US5508219A | SOI DRAM with field-shield isolation and body contact | Electricity | 96 | Expired |
| US6087225A | Method for dual gate oxide dual workfunction CMOS | Electricity | 71 | Expired |
| US5360758A | Self-aligned buried strap for trench type DRAM cells | Electricity | 70 | Expired |
| US5945707A | DRAM cell with grooved transfer device | Electricity | 67 | Expired |
| US6767789B1 | Method for interconnection between transfer devices and storage capacitors in memory cells and device formed thereby | Electricity | 66 | Expired |
| US5876788A | High dielectric TiO.sub.2 -SiN composite films for memory applications | Electricity | 64 | Expired |
| US5792703A | Self-aligned contact wiring process for SI devices | Electricity | 63 | Expired |
| US5362663A | Method of forming double well substrate plate trench DRAM cell array | Electricity | 57 | Expired |
| US6388294B1 | Integrated circuit using damascene gate structure | Electricity | 50 | Expired |
| US6426252B1 | Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap | Electricity | 49 | Expired |
| US6242770A | Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method for forming the same | Performing Operations; Transporting | 46 | Expired |
| US6140208A | Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications | Electricity | 45 | Expired |
| US5128271A | High performance vertical bipolar transistor structure via self-aligning processing techniques | Emerging Cross-Sectional Technologies | 43 | Expired |
| US6194301A | Method of fabricating an integrated circuit of logic and memory using damascene gate structure | Electricity | 42 | Expired |
| US6037194A | Method for making a DRAM cell with grooved transfer device | Electricity | 41 | Expired |
| US5766971A | Oxide strip that improves planarity | Emerging Cross-Sectional Technologies | 41 | Expired |
| US5525531A | SOI DRAM with field-shield isolation | Electricity | 41 | Expired |
| US5250829A | Double well substrate plate trench DRAM cell array | Electricity | 37 | Expired |
| US5253202A | Word line driver circuit for dynamic random access memories | Physics | 34 | Expired |
| US6281064A | Method for providing dual work function doping and protective insulating cap | Electricity | 33 | Expired |
| US8344475B2 | Integrated circuit heating to effect in-situ annealing | Electricity | 32 | Active |
| US6573137B1 | Single sided buried strap | Electricity | 31 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.