Read clock toggle at configurable PAM levels
US12002541B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 30, 2022 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Sep 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.