Power efficient memory value updates for arm architectures
US12007936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2022 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Jan 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/522
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are various examples of providing provide efficient waiting for detection of memory value updates for Advanced RISC Machines (ARM) architectures. An ARM processor component instructs a memory agent to perform a processing action, and executes a waiting function. The waiting function ensures that the processing action is completed by the memory agent. The waiting function performs an exclusive load at a memory location, and a wait for event (WFE) instruction that causes the ARM processor component to wait in a low-power mode for an event register to be set. Once the event register is set, the waiting function completes and a second processing action is executed by the ARM processor component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.