Semiconductor device with reduced critical dimensions
US12009212B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 2021 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Dec 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.