Semiconductor device having planar transistor and FinFET
US12009262B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | May 9, 2022 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Jun 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a FinFET on a first region of a substrate and a planar-FET on a second region of the substrate. The FinFET includes a FinFET source region, a FinFET drain region, and a FinFET gate between the FinFET source region and the FinFET drain region. The planar-FET includes a planar-FET source region, a planar-FET drain region, and a planar-FET gate between the planar-FET source region and the planar-FET drain region. A bottommost position of the FinFET source region is lower than a bottommost position of the planar-FET source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.