DRAM computation circuit and method
US12014768B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2022 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Apr 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes first and second circuits. The first circuit includes a DRAM array including a plurality of bit lines, and the second circuit includes a computation circuit including a sense amplifier circuit. A boundary layer is positioned between the first and second circuits, and the boundary layer includes a plurality of via structures configured to electrically connect the plurality of bit lines to the sense amplifier circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.