Warpage-reducing semiconductor structure and fabricating method of the same
US12014995B2 · kind B2 · utility
1Cited by
1References
8Claims
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Key dates
| Filing date | Jul 7, 2021 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Nov 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.