Structure and material engineering methods for optoelectronic devices signal to noise ratio enhancement
US12015042B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2020 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Apr 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F71/139
Abstract
A method of fabricating a semiconductor device includes forming an interconnect structure over a front side of a sensor substrate, thinning the sensor substrate from a back side of the sensor substrate, etching trenches into the sensor substrate, pre-cleaning an exposed surface of the sensor substrate, epitaxially growing a charge layer directly on the pre-cleaned exposed surface of the sensor substrate, and forming isolation structures within the etched trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.