Triple layer high-k gate dielectric stack for workfunction engineering
US12015066B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2021 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Apr 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.