Dual phase clock distribution from a single source in a die-to-die interface
US12015412B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2022 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Dec 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first die having a phase locked loop outputting a local clock signal and a strobe signal to a first transmit block of the first die. The strobe signal has a phase offset relative to the local clock signal. A second die is aligned with the first die so each of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die. A plurality of connection paths of a substantially same length couple a connection points of the first plurality of connection points to corresponding connection points of the second plurality of connection points. Different connection paths transmit data signals from the first die to the second die based on the local clock signal and transmit the strobe signal from the first die to the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.