Dynamically allocated buffer pooling
US12019908B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2021 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | May 9, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.