Rescheduling a failed memory request in a processor
US12020064B2 · kind B2 · utility
0Cited by
6References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2020 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Oct 19, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices and techniques to reschedule a memory request that has failed when a thread is executing in a processor are described herein. When a memory request for a thread is denied at a point in the execution pipeline of the processor beyond a thread rescheduling point, the thread can be placed into a memory response path of the processor. An indicator that a register write-back will not occur for the thread can also be provided. Then, the thread can be rescheduled with other threads in the memory response path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.