Patent · US Active

Three-dimensional memory devices

US12020750B2 · kind B2 · utility

1Cited by
5References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 21, 2021
Grant dateJun 25, 2024
Priority date
Expiry dateAug 28, 2042

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D88/00
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of memory cells including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells including a second transistor, and a third semiconductor layer in contact with the second transistor. The second semiconductor layer is between the first bonding interface and the first peripheral circuit. The third semiconductor layer is between the second bonding interface and the second peripheral circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.