Memory device and method of manufacturing the same
US12022654B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Feb 25, 2021 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Dec 9, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/20
Abstract
Provided is a memory device including a substrate, a stack structure, a polysilicon layer, a vertical channel structure, and a charge storage structure. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The polysilicon layer is disposed between the substrate and the stack structure. The vertical channel structure penetrates through the stack structure and the polysilicon layer. The charge storage structure is at least disposed between the vertical channel structure and the plurality of conductive layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.