Memory device for performing smart refresh operation by counting received address
US12027193B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | May 7, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include: a memory bank comprising a plurality of memory blocks, each divided into a normal area and a row hammer area, a command control circuit suitable for performing an access operation on the normal area in response to an active command, an internal command generation circuit suitable for generating an internal command in response to a precharge command, a target address generation circuit suitable for saving a count for each logic level combination of a received address in the row hammer area by performing an access operation on the row hammer area in response to the internal command, and setting an address corresponding to the count as a target address when the count satisfies a preset condition, and a refresh control circuit suitable for controlling a smart refresh operation on the target address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.