Low power management for sleep mode operation of a memory device
US12027227B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Dec 22, 2020 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Dec 22, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.