June Lee
42Patents
7h-index
29Co-inventors
69Inventor score
Filing activity: Aug 18, 2003 → May 28, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7280398B1 | System and memory for sequential multi-plane page memory operations | Physics | 118 | Active |
| US7515485B2 | External clock tracking pipelined latch scheme | Physics | 32 | Active |
| US7679961B2 | Programming and/or erasing a memory device in response to its program and/or erase history | Physics | 32 | Active |
| US7920431B2 | Asynchronous/synchronous interface | Emerging Cross-Sectional Technologies | 24 | Active |
| US7489543B1 | Programming multilevel cell memory arrays | Physics | 14 | Active |
| US7383043B2 | Wireless network system capable of tracking a location of a mobile station and a method for tracking a location of the mobile station | Electricity | 13 | Expired |
| US7925910B2 | Systems, methods and devices for limiting current consumption upon power-up | Physics | 8 | Active |
| US7738295B2 | Programming a non-volatile memory device | Physics | 7 | Active |
| US7450462B2 | System and memory for sequential multi-plane page memory operations | Physics | 7 | Active |
| US7292487B1 | Independent polling for multi-page programming | Physics | 6 | Expired |
| US7609565B2 | External clock tracking pipelined latch scheme | Physics | 6 | Active |
| US8199574B2 | Apparatus comparing verified data to original data in the programming of a memory array | Physics | 6 | Active |
| US8194458B2 | Programming and/or erasing a memory device in response to its program and/or erase history | Physics | 4 | Active |
| US8917550B2 | Apparatus comparing verified data to original data in the programming of memory cells | Physics | 3 | Active |
| US9190153B2 | Asynchronous/synchronous interface | Emerging Cross-Sectional Technologies | 3 | Active |
| US8248868B2 | Asynchronous/synchronous interface | Emerging Cross-Sectional Technologies | 3 | Active |
| US8593889B2 | Asynchronous/synchronous interface | Emerging Cross-Sectional Technologies | 3 | Active |
| US7411848B2 | Independent polling for multi-page programming | Physics | 3 | Active |
| US8145866B2 | Selective register reset | Physics | 2 | Active |
| US7580283B2 | System and memory for sequential multi-plane page memory operations | Physics | 2 | Active |
| US9390049B2 | Logical unit address assignment | Physics | 2 | Active |
| US10083725B2 | Asynchronous/synchronous interface | Emerging Cross-Sectional Technologies | 1 | Active |
| US8194450B2 | Methods and control circuitry for programming memory cells | Physics | 1 | Active |
| US7738294B2 | Programming multilevel cell memory arrays | Physics | 1 | Active |
| US12027227B2 | Low power management for sleep mode operation of a memory device | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.