Method for resetting an array of resistive memory cells
US12033698B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Dec 3, 2020 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Apr 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for resetting an array of Resistive Memory cells by applying a sequence of N reset operations, each reset operation including the application of a reset technique, the method including, at the first reset operation, performing the first reset operation by applying the reset technique having the highest relative correction yield; at the j-th reset operation of the N−1 subsequent reset operations, j being an integer number between 2 and N, defining a reset technique to be used at the j-th reset operation and performing the j-th reset operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.