Split read port latch array bit cell
US12033721B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2021 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Jun 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line while sharing a write bit line. The adjacent bit cells include asymmetrical read access circuits that convey data stored by latch circuitry of a corresponding bit cell to a corresponding read bit line. The layout of adjacent bit cells provides a number of contacted gate pitches per bit cell that is less than a sum of the maximum number of metal gates in layout of each of the adjacent bit cells divided by the number of adjacent bit cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.