Selectively roughened copper architectures for low insertion loss conductive features

US12033930B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jieying Kong · Chandler, US
• Yiyang Zhou · Chandler, US
• Suddhasattwa Nad · Chandler, US
• Jeremy Ecton · Gilbert, US
• Hongxia Feng · Chandler, US
• Tarek A. Ibrahim · Mesa, US
• Brandon C. Marin · Chandler, US
• Zhiguo Qian · Chandler, US
• Sarah Blythe · Chandler, US
• Bohan Shan · Chandler, US
• Jason Steill · Phoenix, US
• Sri Chaitra Jyotsna Chavali · Chandler, US
• Leonel Arana · Phoenix, US
• Dingying Xu · Chandler, US
• Marcel Wall · Phoenix, US

Key dates

• Filing date: Sep 25, 2020
• Grant date: Jul 9, 2024
• Expiry date: Nov 7, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/49827
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.