Chemical mechanical polishing for copper dishing control
US12033964B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2021 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Dec 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/29186
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.