Memory devices having vertical transistors and methods for forming the same
US12033967B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2021 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Dec 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells, a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction, and a plurality of word lines coupled to the memory cells and each extending in a third direction perpendicular to the first direction and the second direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the third direction and one side of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.