Combination scheme for baseline wander, direct current level shifting, and receiver linear equalization for high speed links
US12034440B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2021 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Dec 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45475
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.