Three-dimensional memory devices having through stair contacts and methods for forming the same
US12035530B2 · kind B2 · utility
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8References
20Claims
0Family size
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Key dates
| Filing date | Sep 28, 2023 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Sep 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an example, a three-dimensional (3D) memory device includes a memory stack and a through stair contact (TSC). The memory stack includes interleaved conductive layers and dielectric layers. The memory stack includes stairs in a staircase region. The TSC extends through the memory stack in the staircase region. The TSC includes a first conductor layer and a first spacer circumscribing the first conductor layer. The first conductor layer of the TSC is insulated from the conductive layers of the memory stack by the first spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.