Memory array and memory device
US12035532B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2021 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Nov 18, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
Abstract
A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.