Patent · US Active

Technologies for high aspect ratio carbon etching with inserted charge dissipation layer

US12040176B2 · kind B2 · utility

0Cited by

0References

20Claims

0Family size

Assignee

TOKYO ELECTRON LIMITED · JP

Inventors

Shihsheng Chang · Albany, US
Andrew Metz · Albany, US
Yun Han · Albany, US
Minjoon Park · San Jose, US
Ya-Ming Chen · Austin, US

Key dates

Filing date	Mar 28, 2022
Grant date	Jul 16, 2024
Priority date	—
Expiry date	Jul 20, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH10B43/27
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor device structure includes a dielectric layer formed on a silicon substrate, an amorphous carbon layer (ACL) formed on the dielectric layer, and a charge dissipation layer formed between the ACL and the dielectric layer. The charge dissipation layer is formed from a material having a resistivity lower than the resistivity of the ACL. Methodologies to fabricate the semiconductor device structure are also disclosed and include forming the dielectric layer on the silicon substrate, forming the charge dissipation layer on the dielectric layer, and forming the ACL on the charge dissipation layer. Alternative semiconductor device structures and fabrication methodologies are also disclosed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.