Semiconductor memory device and fabrication method thereof
US12040369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2022 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Jun 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A semiconductor memory device includes a substrate, a pair of floating gates disposed on the substrate, a source line doped region in the substrate between the floating gates, an erase gate disposed between the floating gates and on the source line doped region, a word line disposed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate, and a bit line doped region in the substrate and adjacent to the word line. An upper surface of the source line doped region has a concave profile lower than a surface of the substrate and with a radius between 40 nm and 60 nm in a cross-sectional view perpendicular to the floating gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.