High voltage semiconductor device including buried oxide layer
US12040396B2 · kind B2 · utility
0Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2023 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Mar 2, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/013
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.