Plug and recess process for dual metal gate on stacked nanoribbon devices
US12046652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2020 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Nov 23, 2042 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.