Inventor · Hillsboro, OR, US

Michael K. Harper

17Patents
3h-index
47Co-inventors
56Inventor score

Filing activity: May 9, 2006 → Feb 9, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US8441074B2 Substrate fins with different heights Electricity 20 Active
US8193641B2 Recessed workfunction metal in CMOS transistor gates Electricity 18 Active
US8314034B2 Feature size reduction Electricity 4 Active
US8629039B2 Substrate fins with different heights Electricity 3 Active
US8377771B2 Recessed workfunction metal in CMOS transistor gates Electricity 2 Active
US7977248B2 Double patterning with single hard mask Electricity 1 Active
US11972979B2 1D vertical edge blocking (VEB) via and plug Electricity 0 Active
US11990472B2 Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates Electricity 0 Active
US11594637B2 Gate-all-around integrated circuit structures having fin stack isolation Electricity 0 Active
US12046652B2 Plug and recess process for dual metal gate on stacked nanoribbon devices Performing Operations; Transporting 0 Active
US9768249B2 Trigate transistor structure with unrecessed field insulator and thinner electrodes over the field insulator Electricity 0 Active
US9905693B2 Trigate transistor structure with unrecessed field insulator and thinner electrodes over the field insulator Electricity 0 Active
US12369392B2 Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates Electricity 0 Active
US9916988B2 Sacrificial material for stripping masking layers Electricity 0 Active
US11721580B2 1D vertical edge blocking (VEB) via and plug Electricity 0 Active
US11569231B2 Non-planar transistors with channel regions having varying widths Electricity 0 Active
US12068314B2 Fabrication of gate-all-around integrated circuit structures having adjacent island structures Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.