Fiber to chip coupler and method of making the same
US12050348B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2023 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Aug 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/4204
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of making a chip includes depositing a first polysilicon layer on a top surface and a bottom surface of a substrate. The method further includes patterning the first polysilicon layer to define a recess, wherein the first polysilicon layer is completed removed from the recess. The method further includes implanting dopants into the substrate to define an implant region. The method further includes depositing a contact etch stop layer (CESL) in the recess, wherein the CESL covers the implant region. The method further includes patterning the CESL to define a CESL block. The method further includes forming a waveguide and a grating in the substrate. The method further includes forming an interconnect structure over the waveguide, the grating and the CESL block. The method further includes etching the interconnect structure to define a cavity aligned with the grating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.