Method and apparatus to mitigate hot electron read disturbs in 3D nand devices
US12051469B2 · kind B2 · utility
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3References
18Claims
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Key dates
| Filing date | May 26, 2022 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Aug 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.