Electronic package and manufacturing method thereof
US12051641B2 · kind B2 · utility
0Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2021 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | May 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.