Memory comprising a matrix of resistive memory cells, and associated method of interfacing
US12052876B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 13, 2021 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Sep 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a matrix of resistive memory cells and an interfacing device to interface the matrix, the interfacing device including at least a conversion capacitor, an electric source, a first switch and a second switch, the interfacing device being configured to: a) connect the conversion capacitor to the source by the second switch to charge the conversion capacitor, then, b) disconnect the conversion capacitor from the source and connect the conversion capacitor to the matrix to achieve a conversion between, on the one hand, a resistive state of one of the memory cells of the matrix, and, on the other hand, a state of charge of the conversion capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.