Memory device with unique read and/or programming parameters
US12057161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2022 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Dec 6, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage parameter is a VSGD voltage that is applied to a select gate drain transistor during programming. Yet another unique voltage parameter is an inhibit voltage that is applied to a bit line coupled with a memory cell being inhibited from programming while other memory cells are programmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.