Package formation methods including coupling a molded routing layer to an integrated routing layer
US12057364B2 · kind B2 · utility
0Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2022 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Nov 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.