Patent · US Active

Stress relief die implementation

US12057411B2 · kind B2 · utility

0Cited by

9References

25Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Stephan Stoeckl · Schwandorf, DE
Wolfgang Molzer · Ottobrunn, DE
Georg Seidemann · Landshut, DE
Bernd Waidhas · Nittendorf, DE

Key dates

Filing date	Dec 19, 2019
Grant date	Aug 6, 2024
Priority date	—
Expiry date	Apr 22, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2224/16225
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Embodiments disclosed herein include semiconductor packages. In a particular embodiment, the semiconductor package is a wafer level chip scale package (WLCSP). In an embodiment, the WLCSP comprises a die. In an embodiment, the die comprises an active surface and a backside surface. The die has a first coefficient of thermal expansion (CTE). In an embodiment, the WLCSP further comprises a channel into the die. In an embodiment, the channel is filled with a stress relief material, where the stress relief material has a second CTE that is greater than the first CTE.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.