Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates
US12057491B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2019 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Jan 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.