Parity data in dynamic random access memory (DRAM)
US12061518B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2023 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Feb 13, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.