Application of a default shared state cache coherency protocol
US12061552B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 11, 2023 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | May 11, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.