Semiconductor substrate and method of sawing the same
US12062626B2 · kind B2 · utility
0Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 9, 2023 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | May 9, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.